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509 lines
20 KiB
509 lines
20 KiB
/***************************************************************************** |
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* Copyright (c) 2019, Nations Technologies Inc. |
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* |
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* All rights reserved. |
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* **************************************************************************** |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* - Redistributions of source code must retain the above copyright notice, |
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* this list of conditions and the disclaimer below. |
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* |
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* Nations' name may not be used to endorse or promote products derived from |
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* this software without specific prior written permission. |
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* |
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
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* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, |
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, |
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* ****************************************************************************/ |
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/** |
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* @file n32g45x_tsc.h |
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* @author Nations |
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* @version v1.0.1 |
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* |
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* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. |
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*/ |
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#ifndef __N32G45X_TSC_H__ |
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#define __N32G45X_TSC_H__ |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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#include "n32g45x.h" |
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/** @addtogroup N32G45X_StdPeriph_Driver |
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* @{ |
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*/ |
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/** @addtogroup TSC |
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* @{ |
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*/ |
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/** |
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* @brief TSC error code |
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*/ |
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typedef enum { |
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TSC_ERROR_OK = 0x00U, /*!< No error */ |
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TSC_ERROR_CLOCK = 0x01U, /*!< clock config error */ |
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TSC_ERROR_PARAMETER = 0x02U, /*!< parameter error */ |
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TSC_ERROR_HW_MODE = 0x02U, /*!< Exit hw mode timeout */ |
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}TSC_ErrorTypeDef; |
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/** |
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* @ |
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*/ |
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/** |
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* @brief TSC clock source |
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*/ |
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#define TSC_CLK_SRC_LSI (0x00000000) /*!< LSI*/ |
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#define TSC_CLK_SRC_LSE (RCC_LSE_ENABLE) /*!< LSE */ |
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#define TSC_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS) /*!< LSE bypass */ |
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/** |
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* @ |
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*/ |
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/** |
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* @defgroup Detect_Period |
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*/ |
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#define TSC_DET_PERIOD_8 (0x00000000U) /*!< DET_PERIOD[3:0] = 8/TSC_CLOCK */ |
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#define TSC_DET_PERIOD_16 (0x01UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000001U DET_PERIOD[3:0] = 16/TSC_CLOCK */ |
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#define TSC_DET_PERIOD_24 (0x02UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000002U DET_PERIOD[3:0] = 24/TSC_CLOCK */ |
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#define TSC_DET_PERIOD_32 (0x03UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000003U DET_PERIOD[3:0] = 32/TSC_CLOCK(default) */ |
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#define TSC_DET_PERIOD_40 (0x04UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000004U DET_PERIOD[3:0] = 40/TSC_CLOCK */ |
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#define TSC_DET_PERIOD_48 (0x05UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000005U DET_PERIOD[3:0] = 48/TSC_CLOCK */ |
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#define TSC_DET_PERIOD_56 (0x06UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000006U DET_PERIOD[3:0] = 56/TSC_CLOCK */ |
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#define TSC_DET_PERIOD_64 (0x07UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000007U DET_PERIOD[3:0] = 64/TSC_CLOCK */ |
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#define TSC_DET_PERIOD_72 (0x08UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000008U DET_PERIOD[3:0] = 72/TSC_CLOCK */ |
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#define TSC_DET_PERIOD_80 (0x09UL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x00000009U DET_PERIOD[3:0] = 80/TSC_CLOCK */ |
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#define TSC_DET_PERIOD_88 (0x0AUL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x0000000AU DET_PERIOD[3:0] = 88/TSC_CLOCK */ |
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#define TSC_DET_PERIOD_96 (0x0BUL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x0000000BU DET_PERIOD[3:0] = 96/TSC_CLOCK */ |
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#define TSC_DET_PERIOD_104 (0x0CUL << TSC_CTRL_DET_PERIOD_SHIFT) /*!< 0x0000000CU DET_PERIOD[3:0] = 104/TSC_CLOCK */ |
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/** |
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* @ |
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*/ |
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/** |
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* @defgroup Detect_Filter |
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*/ |
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#define TSC_DET_FILTER_1 (0x00000000U) /*!< DET_FILTER[3:0] = 1 sample */ |
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#define TSC_DET_FILTER_2 (0x01UL << TSC_CTRL_DET_FILTER_SHIFT) /*!< 0x00000010U DET_FILTER[3:0] = 2 samples */ |
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#define TSC_DET_FILTER_3 (0x02UL << TSC_CTRL_DET_FILTER_SHIFT) /*!< 0x00000020U DET_FILTER[3:0] = 3 samples */ |
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#define TSC_DET_FILTER_4 (0x03UL << TSC_CTRL_DET_FILTER_SHIFT) /*!< 0x00000030U DET_FILTER[3:0] = 4 samples */ |
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/** |
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* @ |
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*/ |
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/** |
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* @defgroup HW_Detect_Mode |
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*/ |
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#define TSC_HW_DET_MODE_DISABLE (0x00000000U) /*!< Hardware detect mode disable */ |
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#define TSC_HW_DET_MODE_ENABLE (0x01UL << TSC_CTRL_HW_DET_MODE_SHIFT) /*!< 0x00000040U Hardware detect mode enable */ |
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/** |
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* @ |
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*/ |
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/** |
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* @defgroup Detect_Type |
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*/ |
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#define TSC_DET_TYPE_MASK (TSC_CTRL_LESS_DET_SEL_MASK|TSC_CTRL_GREAT_DET_SEL_MASK) |
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#define TSC_DET_TYPE_SHIFT (TSC_CTRL_LESS_DET_SEL_SHIFT) |
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#define TSC_DET_TYPE_NONE (0UL) /*!< 0x00000000U Disable detect */ |
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#define TSC_DET_TYPE_LESS (0x01UL << TSC_DET_TYPE_SHIFT) /*!< 0x00000100U Less detect enable */ |
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#define TSC_DET_TYPE_GREAT (0x02UL << TSC_DET_TYPE_SHIFT) /*!< 0x00000200U Great detect enable */ |
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#define TSC_DET_TYPE_PERIOD (0x03UL << TSC_DET_TYPE_SHIFT) /*!< 0x00000300U Both great and less detct enable */ |
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/** |
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* @ |
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*/ |
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/** |
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* @defgroup TSC_Interrupt |
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*/ |
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#define TSC_IT_DET_ENABLE (TSC_CTRL_DET_INTEN) /*!< Enable TSC detect interrupt */ |
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#define TSC_IT_DET_DISABLE (0UL) /*!< Disable TSC detect interrupt */ |
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/** |
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* @ |
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*/ |
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/** |
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* @defgroup TSC_Out |
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*/ |
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#define TSC_OUT_PIN (0x00000000U) /*!< TSC output to TSC_OUT pin */ |
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#define TSC_OUT_TIM4_ETR (0x1UL << TSC_CTRL_TM4_ETR_SHIFT) /*!< TSC output to TIM4 ETR */ |
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#define TSC_OUT_TIM2_ETR (0x2UL << TSC_CTRL_TM4_ETR_SHIFT) /*!< TSC output to TIM2 ETR and TIM2 CH1*/ |
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/** |
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* @ |
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*/ |
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/** |
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* @defgroup TSC_Flag |
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*/ |
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#define TSC_FLAG_HW (0x1UL << TSC_CTRL_HW_DET_ST_SHIFT) /*!< Flag of hardware detect mode */ |
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#define TSC_FLAG_GREAT_DET (0x1UL << TSC_STS_GREAT_DET_SHIFT) /*!< Flag of great detect type */ |
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#define TSC_FLAG_LESS_DET (0x1UL << TSC_STS_LESS_DET_SHIFT) /*!< Flag of less detect type */ |
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#define TSC_FLAG_PERIOD_DET (TSC_FLAG_GREAT_DET|TSC_FLAG_LESS_DET) /*!< Flag of period detect type */ |
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/** |
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* @ |
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*/ |
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/** |
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* @defgroup TSC_SW_Detect |
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*/ |
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#define TSC_SW_MODE_DISABLE (0x00000000U) /*!< Disable software detect mode */ |
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#define TSC_SW_MODE_ENABLE (0x1UL << TSC_ANA_CTRL_SW_TSC_EN_SHIFT) /*!< Enable software detect mode */ |
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/** |
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* @ |
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*/ |
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/** |
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* @defgroup TSC_PadOption |
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*/ |
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#define TSC_PAD_INTERNAL_RES (0x00000000U) /*!< Use internal resistor */ |
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#define TSC_PAD_EXTERNAL_RES (0x1UL << TSC_ANA_SEL_PAD_OPT_SHIFT) /*!< Use external resistor */ |
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/** |
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* @ |
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*/ |
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/** |
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* @defgroup TSC_PadSpeed |
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*/ |
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#define TSC_PAD_SPEED_0 (0x00000000U) /*!< Low speed,about 100K */ |
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#define TSC_PAD_SPEED_1 (0x1UL << TSC_ANA_SEL_SP_OPT_SHIFT) /*!< Middle spped */ |
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#define TSC_PAD_SPEED_2 (0x2UL << TSC_ANA_SEL_SP_OPT_SHIFT) /*!< Middle spped */ |
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#define TSC_PAD_SPEED_3 (0x3UL << TSC_ANA_SEL_SP_OPT_SHIFT) /*!< Middle spped */ |
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/** |
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* @ |
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*/ |
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/** |
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* @defgroup TSC_Constant |
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*/ |
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#define TSC_CHN_SEL_ALL (TSC_CHNEN_CHN_SEL_MASK) |
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#define MAX_TSC_HW_CHN (24) /*Maximum number of tsc pin*/ |
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#define MAX_TSC_THRESHOLD_BASE (2047) /*Maximum detect base value of threshold*/ |
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#define MAX_TSC_THRESHOLD_DELTA (255) /*Maximum detect delta value of threshold*/ |
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#define TSC_TIMEOUT (SystemCoreClock>>4) /*TSC normal timeout */ |
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/** |
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* @ |
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*/ |
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/** |
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* @defgroup TSC_DetectMode |
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*/ |
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#define TSC_HW_DETECT_MODE (0x00000001U) /*TSC hardware detect mode*/ |
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#define TSC_SW_DETECT_MODE (0x00000000U) /*TSC software detect mode*/ |
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/** |
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* @ |
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*/ |
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/* TSC Exported macros -----------------------------------------------------------*/ |
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/** @defgroup TSC_Exported_Macros |
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* @{ |
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*/ |
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/** @brief Enable the TSC HW detect mode |
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* @param None |
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* @retval None |
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*/ |
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#define __TSC_HW_ENABLE() SET_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE) |
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/** @brief Disable the TSC HW detect mode |
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* @param None |
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* @retval None |
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*/ |
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#define __TSC_HW_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE) |
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/** @brief Config TSC detect period for HW detect mode |
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* @param __PERIOD__ specifies the TSC detect period during HW detect mode |
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* @arg TSC_DET_PERIOD_8: Detect period = 8/TSC_CLK |
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* @arg TSC_DET_PERIOD_16: Detect Period = 1/TSC_CLK |
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* @arg TSC_DET_PERIOD_24: Detect Period = 2/TSC_CLK |
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* @arg TSC_DET_PERIOD_32: Detect Period = 3/TSC_CLK |
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* @arg TSC_DET_PERIOD_40: Detect Period = 4/TSC_CLK |
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* @arg TSC_DET_PERIOD_48: Detect Period = 5/TSC_CLK |
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* @arg TSC_DET_PERIOD_56: Detect Period = 6/TSC_CLK |
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* @arg TSC_DET_PERIOD_64: Detect Period = 7/TSC_CLK |
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* @arg TSC_DET_PERIOD_72: Detect Period = 7/TSC_CLK |
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* @arg TSC_DET_PERIOD_80: Detect Period = 7/TSC_CLK |
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* @arg TSC_DET_PERIOD_88: Detect Period = 7/TSC_CLK |
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* @arg TSC_DET_PERIOD_96: Detect Period = 7/TSC_CLK |
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* @arg TSC_DET_PERIOD_104:Detect Period = 7/TSC_CLK |
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* @retval None |
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*/ |
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#define __TSC_PERIOD_CONFIG(__PERIOD__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_PERIOD_MASK,__PERIOD__) |
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/** @brief Config TSC detect filter for HW detect mode |
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* @param __FILTER__ specifies the least usefull continuous samples during HW detect mode |
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* @arg TSC_DET_FILTER_1: Detect filter = 1 pulse |
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* @arg TSC_DET_FILTER_2: Detect filter = 2 pulse |
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* @arg TSC_DET_FILTER_3: Detect filter = 3 pulse |
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* @arg TSC_DET_FILTER_4: Detect filter = 4 pulse |
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* @retval None |
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*/ |
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#define __TSC_FILTER_CONFIG(__FILTER__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_FILTER_MASK,__FILTER__) |
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/** @brief Config TSC detect type for HW detect mode,less great or both |
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* @param __TYPE__ specifies the detect type of a sample during HW detect mode |
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* @arg TSC_DET_TYPE_NONE: Detect disable |
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* @arg TSC_DET_TYPE_LESS: Pulse number must be greater than the threshold(basee-delta) during a sample time |
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* @arg TSC_DET_TYPE_GREAT: Pulse number must be less than the threshold(basee+delta) during a sample time |
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* @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta) |
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and also be less than (basee+delta) during a sample time |
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* @retval None |
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*/ |
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#define __TSC_LESS_GREAT_CONFIG(__TYPE__) MODIFY_REG(TSC->CTRL, \ |
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(TSC_CTRL_LESS_DET_SEL_MASK|TSC_CTRL_GREAT_DET_SEL_MASK), \ |
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__TYPE__) |
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/** @brief Enable TSC interrupt |
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* @param None |
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* @retval None |
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*/ |
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#define __TSC_INT_ENABLE() SET_BIT(TSC->CTRL, TSC_IT_DET_ENABLE) |
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/** @brief Disable TSC interrupt |
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* @param None |
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* @retval None |
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*/ |
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#define __TSC_INT_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_IT_DET_ENABLE) |
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/** @brief Config the TSC output |
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* @param __OUT__ specifies where the TSC output should go |
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* @arg TSC_OUT_PIN: TSC output to the TSC_OUT pin |
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* @arg TSC_OUT_TIM4_ETR: TSC output to TIM4 as ETR |
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* @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR |
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* @retval None |
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*/ |
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#define __TSC_OUT_CONFIG(__OUT__) MODIFY_REG( TSC->CTRL, \ |
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(TSC_CTRL_TM4_ETR_MASK|TSC_CTRL_TM2_ETR_CH1_MASK),\ |
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__OUT__) |
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/** @brief Config the TSC channel |
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* @param __CHN__ specifies the pin of channels used for detect |
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* This parameter:bit[0:23] used,bit[24:31] must be 0 |
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* bitx: TSC channel x |
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* @retval None |
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*/ |
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#define __TSC_CHN_CONFIG(__CHN__) WRITE_REG(TSC->CHNEN, __CHN__) |
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/** @brief Enable the TSC SW detect mode |
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* @param None |
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* @retval None |
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*/ |
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#define __TSC_SW_ENABLE() SET_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN) |
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/** @brief Disable the TSC SW detect mode |
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* @param None |
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* @retval None |
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*/ |
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#define __TSC_SW_DISABLE() CLEAR_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN) |
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/** @brief Config the detect channel number during SW detect mode |
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* @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN |
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* @retval None |
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*/ |
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#define __TSC_SW_CHN_NUM_CONFIG(__NUM__) MODIFY_REG(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_PAD_MUX_MASK,__NUM__) |
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/** @brief Config the pad charge type |
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* @param __OPT__ specifies which resistor is used for charge |
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* @arg TSC_PAD_INTERNAL_RES: Internal resistor is used |
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* @arg TSC_PAD_EXTERNAL_RES: External resistor is used |
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* @retval None |
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*/ |
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#define __TSC_PAD_OPT_CONFIG(__OPT__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_PAD_OPT_MASK,__OPT__) |
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/** @brief Config TSC speed |
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* @param __SPEED__ specifies the TSC speed range |
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* @arg TSC_PAD_SPEED_0: Low speed |
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* @arg TSC_PAD_SPEED_1: Middle speed |
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* @arg TSC_PAD_SPEED_2: Middle speed |
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* @arg TSC_PAD_SPEED_3: High speed |
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* @retval None |
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*/ |
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#define __TSC_PAD_SPEED_CONFIG(__SPEED__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_SP_OPT_MASK,__SPEED__) |
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/** @brief Check if the HW detect mode is enable |
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* @param None |
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* @retval Current state of HW detect mode |
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*/ |
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#define __TSC_GET_HW_MODE() (((TSC->CTRL) & TSC_FLAG_HW) == (TSC_FLAG_HW)) |
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/** @brief Check the detect type during HW detect mode |
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* @param __FLAG__ specifies the flag of detect type |
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* @arg TSC_FLAG_LESS_DET: Flag of less detect type |
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* @arg TSC_FLAG_GREAT_DET: Flag of great detect type |
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* @arg TSC_FLAG_PERIOD_DET: Flag of priod detect type |
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* @retval Current state of flag |
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*/ |
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#define __TSC_GET_HW_DET_TYPE(__FLAG__) (((TSC->STS) & (__FLAG__))==(__FLAG__)) |
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/** @brief Get the number of channel which is detected now |
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* @param None |
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* @retval Current channel number |
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*/ |
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#define __TSC_GET_CHN_NUMBER() (((TSC->STS) & TSC_STS_CHN_NUM_MASK) >> TSC_STS_CHN_NUM_SHIFT ) |
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/** @brief Get the count value of pulse |
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* @param None |
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* @retval Pulse count of current channel |
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*/ |
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#define __TSC_GET_CHN_CNT() (((TSC->STS) & TSC_STS_CNT_VAL_MASK ) >> TSC_STS_CNT_VAL_SHIFT ) |
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/** @brief Get the base value of one channel |
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* @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN |
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* @retval base value of the channel |
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*/ |
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#define __TSC_GET_CHN_BASE(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHD_BASE_MASK ) >> TSC_THRHD_BASE_SHIFT) |
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/** @brief Get the delta value of one channel |
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* @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN |
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* @retval delta value of the channel |
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*/ |
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#define __TSC_GET_CHN_DELTA(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHD_DELTA_MASK ) >> TSC_THRHD_DELTA_SHIFT ) |
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/** @brief Get the internal resist value of one channel |
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* @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN |
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* @retval resist value of the channel |
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*/ |
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#define __TSC_GET_CHN_RESIST(__NUM__) ((TSC->RESR[(__NUM__)>>3] >>(((__NUM__) & 0x7UL)*4)) & TSC_RESR_CHN_RESIST_MASK) |
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/* Private macros ------------------------------------------------------------*/ |
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/** @defgroup TSC_Private_Macros |
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* @{ |
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*/ |
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#define IS_TSC_DET_PERIOD(_PERIOD_) \ |
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(((_PERIOD_)==TSC_DET_PERIOD_8) ||((_PERIOD_)==TSC_DET_PERIOD_16)||((_PERIOD_)==TSC_DET_PERIOD_24) \ |
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||((_PERIOD_)==TSC_DET_PERIOD_32)||((_PERIOD_)==TSC_DET_PERIOD_40)||((_PERIOD_)==TSC_DET_PERIOD_48) \ |
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||((_PERIOD_)==TSC_DET_PERIOD_56)||((_PERIOD_)==TSC_DET_PERIOD_64)||((_PERIOD_)==TSC_DET_PERIOD_72) \ |
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||((_PERIOD_)==TSC_DET_PERIOD_80)||((_PERIOD_)==TSC_DET_PERIOD_88)||((_PERIOD_)==TSC_DET_PERIOD_96) \ |
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||((_PERIOD_)==TSC_DET_PERIOD_104) ) |
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#define IS_TSC_FILTER(_FILTER_) \ |
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( ((_FILTER_)==TSC_DET_FILTER_1) ||((_FILTER_)==TSC_DET_FILTER_2)\ |
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||((_FILTER_)==TSC_DET_FILTER_3) ||((_FILTER_)==TSC_DET_FILTER_4) ) |
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#define IS_TSC_DET_MODE(_MODE_) \ |
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( ((_MODE_)==TSC_HW_DETECT_MODE) ||((_MODE_)==TSC_SW_DETECT_MODE) ) |
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#define IS_TSC_DET_TYPE(_TYPE_) \ |
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( ((_TYPE_)==TSC_DET_TYPE_GREAT) ||((_TYPE_)==TSC_DET_TYPE_LESS) \ |
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||((_TYPE_)==TSC_DET_TYPE_PERIOD)|| ((_TYPE_)==TSC_DET_TYPE_NONE) ) |
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#define IS_TSC_INT(_INT_) (((_INT_)==TSC_IT_DET_ENABLE)||((_INT_)==TSC_IT_DET_DISABLE)) |
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#define IS_TSC_OUT(_ETR_) (((_ETR_)==TSC_OUT_PIN)||((_ETR_)==TSC_OUT_TIM2_ETR)||((_ETR_)==TSC_OUT_TIM4_ETR)) |
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#define IS_TSC_CHN(_CHN_) (0==((_CHN_)&(~TSC_CHNEN_CHN_SEL_MASK))) |
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#define IS_TSC_CHN_NUMBER(_NUM_) ((uint32_t)(_NUM_)<MAX_TSC_HW_CHN) |
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#define IS_TSC_PAD_OPTION(_OPT_) (((_OPT_)==TSC_PAD_INTERNAL_RES)||((_OPT_)==TSC_PAD_EXTERNAL_RES)) |
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#define IS_TSC_PAD_SPEED(_SPEED_) \ |
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( ((_SPEED_)==TSC_PAD_SPEED_0)||((_SPEED_)==TSC_PAD_SPEED_1) \ |
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||((_SPEED_)==TSC_PAD_SPEED_2)||((_SPEED_)==TSC_PAD_SPEED_3) ) |
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#define IS_TSC_RESISTOR_VALUE(_RES_) \ |
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( ((_RES_)==TSC_RESR_CHN_RESIST_1M) ||((_RES_)==TSC_RESR_CHN_RESIST_875K) \ |
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||((_RES_)==TSC_RESR_CHN_RESIST_750K)||((_RES_)==TSC_RESR_CHN_RESIST_625K) \ |
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||((_RES_)==TSC_RESR_CHN_RESIST_500K)||((_RES_)==TSC_RESR_CHN_RESIST_375K) \ |
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||((_RES_)==TSC_RESR_CHN_RESIST_250K)||((_RES_)==TSC_RESR_CHN_RESIST_125K) ) |
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#define IS_TSC_THRESHOLD_BASE(_BASE_) ( (_BASE_)<=MAX_TSC_THRESHOLD_BASE) |
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#define IS_TSC_THRESHOLD_DELTA(_DELTA_) ( (_DELTA_)<=MAX_TSC_THRESHOLD_DELTA) |
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/** |
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* @brief TSC Init structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t Mode; /*!< Configures the TSC work mode. |
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This parameter can be one value of @ref TSC_DetectMode */ |
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uint32_t Period; /*!< Configures the TSC check period for a sample. |
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This parameter can be one value of @ref Detect_Period */ |
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uint32_t Filter; /*!< Configures the TSC filter. |
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This parameter can be one value of @ref Detect_Filter */ |
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uint32_t Type; /*!< Configures the TSC check type |
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This parameter can be one value of @ref Detect_Type */ |
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uint32_t Chn; /*!< Selects the TSC chnnel used |
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This parameter can be one value of @ref TSC_CHNEN_CHN_SELx_MASK */ |
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uint32_t Out; /*!< Configures the TSC_OUT etr |
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This parameter can be one value of @ref TSC_Out */ |
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uint32_t Int; /*!< Configures the TSC interrupt |
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This parameter can be one value of @ref TSC_Interrupt */ |
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uint32_t PadOpt; /*!< Configures the TSC charge resistor |
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This parameter can be one value of @ref TSC_PadOption */ |
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uint32_t Speed; /*!< Configures the TSC detect speed |
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This parameter can be one value of @ref TSC_PadSpeed */ |
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}TSC_InitType; |
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typedef struct |
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{ |
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uint16_t TSC_Base; /*!< base value */ |
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uint8_t TSC_Delta; /*!< offset value */ |
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uint8_t TSC_Resistor; /*!< resistance value configuration*/ |
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} TSC_ChnCfg; |
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/** |
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* @brief define tsc status type |
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*/ |
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typedef enum |
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{ |
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TSC_ALG_STS_CNTVALUE = 0, ///< tsc count of hardware detect |
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TSC_ALG_STS_LESS_DET = 1, ///< tsc less flag of hardware detect |
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TSC_ALG_STS_GREAT_DET = 2, ///< tsc great flag of hardware detect |
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TSC_ALG_STS_CHN_NUM = 3, ///< tsc chn number of hardware detect |
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TSC_ALG_DET_DET_ST = 4, ///< tsc hw detect mode start status |
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} TSC_Status; |
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/** |
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* @brief Analog parameter configuration |
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*/ |
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typedef struct |
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{ |
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uint8_t TSC_AnaoptrSpeedOption; // speed option |
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uint8_t TSC_AnaoptrResisOption; // internal or external resistance option select |
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} TSC_AnaoCfg; |
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TSC_ErrorTypeDef TSC_Init(TSC_InitType* TSC_Init); |
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TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource); |
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TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res ); |
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TSC_ErrorTypeDef TSC_ConfigThreshold( uint32_t Channels, uint32_t base, uint32_t delta); |
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TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_ChnCfg* ChnCfg, uint32_t ChannelNum); |
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uint32_t TSC_GetStatus(TSC_Module* TSC_Def, TSC_Status type); |
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void TSC_Cmd(TSC_Module* TSC_Def, uint32_t Channels, FunctionalState Cmd); |
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void TSC_SW_SwtichChn(TSC_Module* TSC_Def, uint32_t Channel, TIM_Module* TIMx, FunctionalState Cmd); |
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void TSC_SetAnaoCfg(TSC_Module* TSC_Def, TSC_AnaoCfg* AnaoCfg); |
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void TSC_SetChannelCfg(TSC_Module* TSC_Def, TSC_ChnCfg* ChnCfg, uint32_t Channels); |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* __N32G45X_TSC_H__ */ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/
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