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333 lines
12 KiB
333 lines
12 KiB
/***************************************************************************** |
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* Copyright (c) 2019, Nations Technologies Inc. |
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* |
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* All rights reserved. |
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* **************************************************************************** |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* - Redistributions of source code must retain the above copyright notice, |
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* this list of conditions and the disclaimer below. |
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* |
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* Nations' name may not be used to endorse or promote products derived from |
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* this software without specific prior written permission. |
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* |
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
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* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, |
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, |
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* ****************************************************************************/ |
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/** |
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* @file n32g45x_qspi.h |
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* @author Nations |
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* @version v1.0.1 |
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* |
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* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. |
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*/ |
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#ifndef __N32G45X_QSPI_H__ |
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#define __N32G45X_QSPI_H__ |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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#include "n32g45x.h" |
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#include <stdbool.h> |
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/** @addtogroup N32G45X_StdPeriph_Driver |
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* @{ |
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*/ |
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/** @addtogroup QSPI |
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* @brief QSPI driver modules |
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* @{ |
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*/ |
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//////////////////////////////////////////////////////////////////////////////////////////////////// |
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typedef enum |
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{ |
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STANDARD_SPI_FORMAT_SEL = 0, |
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DUAL_SPI_FORMAT_SEL, |
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QUAD_SPI_FORMAT_SEL, |
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XIP_SPI_FORMAT_SEL |
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} QSPI_FORMAT_SEL; |
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typedef enum |
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{ |
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TX_AND_RX = 0, |
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TX_ONLY, |
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RX_ONLY |
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} QSPI_DATA_DIR; |
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typedef enum |
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{ |
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QSPI_NSS_PORTA_SEL, |
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QSPI_NSS_PORTC_SEL, |
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QSPI_NSS_PORTF_SEL |
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} QSPI_NSS_PORT_SEL; |
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typedef enum |
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{ |
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QSPI_NULL = 0, |
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QSPI_SUCCESS, |
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} QSPI_STATUS; |
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//////////////////////////////////////////////////////////////////////////////////////////////////// |
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typedef struct |
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{ |
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/*QSPI_CTRL0*/ |
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uint32_t DFS; |
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uint32_t FRF; |
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uint32_t SCPH; |
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uint32_t SCPOL; |
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uint32_t TMOD; |
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uint32_t SSTE; |
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uint32_t CFS; |
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uint32_t SPI_FRF; |
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/*QSPI_CTRL1*/ |
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uint32_t NDF; |
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/*QSPI_MW_CTRL*/ |
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uint32_t MWMOD; |
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uint32_t MC_DIR; |
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uint32_t MHS_EN; |
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/*QSPI_BAUD*/ |
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uint32_t CLK_DIV; |
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/*QSPI_TXFT*/ |
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uint32_t TXFT; |
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/*QSPI_RXFT*/ |
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uint32_t RXFT; |
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/*QSPI_TXFN*/ |
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uint32_t TXFN; |
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/*QSPI_RXFN*/ |
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uint32_t RXFN; |
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/*QSPI_RS_DELAY*/ |
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uint32_t SDCN; |
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uint32_t SES; |
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/*QSPI_ENH_CTRL0*/ |
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uint32_t ENHANCED_TRANS_TYPE; |
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uint32_t ENHANCED_ADDR_LEN; |
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uint32_t ENHANCED_MD_BIT_EN; |
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uint32_t ENHANCED_INST_L; |
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uint32_t ENHANCED_WAIT_CYCLES; |
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uint32_t ENHANCED_SPI_DDR_EN; |
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uint32_t ENHANCED_INST_DDR_EN; |
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uint32_t ENHANCED_XIP_DFS_HC; |
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uint32_t ENHANCED_XIP_INST_EN; |
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uint32_t ENHANCED_XIP_CT_EN; |
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uint32_t ENHANCED_XIP_MBL; |
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uint32_t ENHANCED_CLK_STRETCH_EN; |
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/*QSPI_DDR_TXDE*/ |
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uint32_t TXDE; |
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/*QSPI_XIP_MODE*/ |
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uint32_t XIP_MD_BITS; |
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/*QSPI_XIP_INCR_TOC*/ |
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uint32_t ITOC; |
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/*QSPI_XIP_WRAP_TOC*/ |
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uint32_t WTOC; |
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/*QSPI_XIP_CTRL*/ |
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uint32_t XIP_FRF; |
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uint32_t XIP_TRANS_TYPE; |
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uint32_t XIP_ADDR_LEN; |
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uint32_t XIP_INST_L; |
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uint32_t XIP_MD_BITS_EN; |
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uint32_t XIP_WAIT_CYCLES; |
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uint32_t XIP_DFS_HC; |
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uint32_t XIP_DDR_EN; |
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uint32_t XIP_INST_DDR_EN; |
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uint32_t XIP_INST_EN; |
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uint32_t XIP_CT_EN; |
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uint32_t XIP_MBL; |
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/*QSPI_XIP_TOUT*/ |
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uint32_t XTOUT; |
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} QSPI_InitType; |
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//////////////////////////////////////////////////////////////////////////////////////////////////// |
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#define QSPI_TIME_OUT_CNT 200 |
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#define IS_QSPI_SPI_FRF(SPI_FRF) \ |
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(((SPI_FRF) == QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT) || ((SPI_FRF) == QSPI_CTRL0_SPI_FRF_DUAL_FORMAT) || ((SPI_FRF) == QSPI_CTRL0_SPI_FRF_QUAD_FORMAT)) |
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#define IS_QSPI_CFS(CFS) ((((CFS) >= QSPI_CTRL0_CFS_2_BIT) && ((CFS) <= QSPI_CTRL0_CFS_16_BIT)) || ((CFS) == QSPI_CTRL0_CFS_1_BIT)) |
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#define IS_QSPI_SSTE(SSTE) (((SSTE) == QSPI_CTRL0_SSTE_EN) || ((SSTE) == 0)) |
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#define IS_QSPI_TMOD(TMOD) \ |
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(((TMOD) == QSPI_CTRL0_TMOD_TX_AND_RX) || ((TMOD) == QSPI_CTRL0_TMOD_TX_ONLY) || ((TMOD) == QSPI_CTRL0_TMOD_RX_ONLY) || ((TMOD) == QSPI_CTRL0_TMOD_EEPROM_READ)) |
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#define IS_QSPI_SCPOL(SCPOL) (((SCPOL) == QSPI_CTRL0_SCPOL_LOW) || ((SCPOL) == QSPI_CTRL0_SCPOL_HIGH)) |
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#define IS_QSPI_SCPH(SCPH) (((SCPH) == QSPI_CTRL0_SCPH_FIRST_EDGE) || ((SCPH) == QSPI_CTRL0_SCPH_SECOND_EDGE)) |
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#define IS_QSPI_FRF(FRF) (((FRF) == QSPI_CTRL0_FRF_MOTOROLA) || ((FRF) == QSPI_CTRL0_FRF_TI) || ((FRF) == QSPI_CTRL0_FRF_MICROWIRE)) |
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#define IS_QSPI_DFS(DFS) (((DFS) >= QSPI_CTRL0_DFS_4_BIT) && ((DFS) <= QSPI_CTRL0_DFS_32_BIT)) |
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#define IS_QSPI_NDF(NDF) (((NDF) <= 0xFFFF)) |
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#define IS_QSPI_MWMOD(MWMOD) (((MWMOD) == QSPI_MW_CTRL_MWMOD_UNSEQUENTIAL) || ((MWMOD) == QSPI_MW_CTRL_MWMOD_SEQUENTIAL)) |
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#define IS_QSPI_MC_DIR(MC_DIR) (((MC_DIR) == QSPI_MW_CTRL_MC_DIR_RX) || ((MC_DIR) == QSPI_MW_CTRL_MC_DIR_TX)) |
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#define IS_QSPI_MHS_EN(MHS_EN) (((MHS_EN) == QSPI_MW_CTRL_MHS_EN) || ((MHS_EN) == 0)) |
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#define IS_QSPI_CLK_DIV(CLK_DIV) (((CLK_DIV) <= 0xFFFF)) |
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#define IS_QSPI_TXFT(TXFT) (((TXFT) <= 0x1FFFFF)) |
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#define IS_QSPI_RXFT(RXFT) (((RXFT) <= 0x1F)) |
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#define IS_QSPI_TXFN(TXFN) (((TXFN) <= 0x3F)) |
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#define IS_QSPI_RXFN(RXFN) (((RXFN) <= 0x3F)) |
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#define IS_QSPI_DMA_CTRL(DMA_CTRL) (((DMA_CTRL) == QSPI_DMA_CTRL_TX_DMA_EN) || ((DMA_CTRL) == QSPI_DMA_CTRL_RX_DMA_EN)) |
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#define IS_QSPI_DMATDL_CTRL(DMATDL_CTRL) (((DMATDL_CTRL) <= 0x3F)) |
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#define IS_QSPI_DMARDL_CTRL(DMARDL_CTRL) (((DMARDL_CTRL) <= 0x3F)) |
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#define IS_QSPI_SES(SES) (((SES) == QSPI_RS_DELAY_SES_RISING_EDGE) || ((SES) == QSPI_RS_DELAY_SES_FALLING_EDGE)) |
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#define IS_QSPI_SDCN(SDCN) (((SDCN) <= 0xFF)) |
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#define IS_QSPI_ENH_CLK_STRETCH_EN(ENH_CLK_STRETCH_EN) (((ENH_CLK_STRETCH_EN) == QSPI_ENH_CTRL0_CLK_STRETCH_EN) || ((ENH_CLK_STRETCH_EN) == 0)) |
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#define IS_QSPI_ENH_XIP_MBL(ENH_XIP_MBL) \ |
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(((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_2_BIT) || ((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_4_BIT) || \ |
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((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_8_BIT) || ((ENH_XIP_MBL) == QSPI_ENH_CTRL0_XIP_MBL_16_BIT)) |
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#define IS_QSPI_ENH_XIP_CT_EN(ENH_XIP_CT_EN) (((ENH_XIP_CT_EN) == QSPI_ENH_CTRL0_XIP_CT_EN) || ((ENH_XIP_CT_EN) == 0)) |
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#define IS_QSPI_ENH_XIP_INST_EN(ENH_XIP_INST_EN) (((ENH_XIP_INST_EN) == QSPI_ENH_CTRL0_XIP_INST_EN) || ((ENH_XIP_INST_EN) == 0)) |
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#define IS_QSPI_ENH_XIP_DFS_HC(ENH_XIP_DFS_HC) (((ENH_XIP_DFS_HC) == QSPI_ENH_CTRL0_XIP_DFS_HC) || ((ENH_XIP_DFS_HC) == 0)) |
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#define IS_QSPI_ENH_INST_DDR_EN(ENH_INST_DDR_EN) (((ENH_INST_DDR_EN) == QSPI_ENH_CTRL0_INST_DDR_EN) || ((ENH_INST_DDR_EN) == 0)) |
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#define IS_QSPI_ENH_SPI_DDR_EN(ENH_SPI_DDR_EN) (((ENH_SPI_DDR_EN) == QSPI_ENH_CTRL0_SPI_DDR_EN) || ((ENH_SPI_DDR_EN) == 0)) |
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#define IS_QSPI_ENH_WAIT_CYCLES(ENH_WAIT_CYCLES) ((((ENH_WAIT_CYCLES) >= QSPI_ENH_CTRL0_WAIT_1CYCLES) && ((ENH_WAIT_CYCLES) <= QSPI_ENH_CTRL0_WAIT_31CYCLES)) || \ |
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((ENH_WAIT_CYCLES) == 0)) |
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#define IS_QSPI_ENH_INST_L(ENH_INST_L) \ |
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(((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_0_LINE) || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_4_LINE) || \ |
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((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_8_LINE) || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_16_LINE)) |
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#define IS_QSPI_ENH_MD_BIT_EN(ENH_MD_BIT_EN) (((ENH_MD_BIT_EN) == QSPI_ENH_CTRL0_MD_BIT_EN) || ((ENH_MD_BIT_EN) == 0)) |
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#define IS_QSPI_ENH_ADDR_LEN(ENH_ADDR_LEN) ((((ENH_ADDR_LEN) >= QSPI_ENH_CTRL0_ADDR_LEN_4_BIT) && ((ENH_ADDR_LEN) <= QSPI_ENH_CTRL0_ADDR_LEN_60_BIT)) || \ |
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((ENH_ADDR_LEN) == 0)) |
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#define IS_QSPI_ENH_TRANS_TYPE(ENH_TRANS_TYPE) (((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD) || \ |
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((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF) || \ |
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((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF)) |
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#define IS_QSPI_DDR_TXDE(DDR_TXDE) (((DDR_TXDE) <= 0xFF)) |
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#define IS_QSPI_XIP_MODE(XIP_MODE) (((XIP_MODE) <= 0xFFFF)) |
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#define IS_QSPI_XIP_INCR_TOC(XIP_INCR_TOC) (((XIP_INCR_TOC) <= 0xFFFF)) |
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#define IS_QSPI_XIP_WRAP_TOC(XIP_WRAP_TOC) (((XIP_WRAP_TOC) <= 0xFFFF)) |
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#define IS_QSPI_XIP_TOUT(XIP_TOUT) (((XIP_TOUT) <= 0xFF)) |
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#define IS_QSPI_XIP_MBL(XIP_MBL) \ |
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(((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_2_BIT) || ((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_4_BIT) || \ |
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((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_8_BIT) || ((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_16_BIT)) |
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#define IS_QSPI_XIP_CT_EN(XIP_CT_EN) (((XIP_CT_EN) == QSPI_XIP_CTRL_XIP_CT_EN) || ((XIP_CT_EN) == 0)) |
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#define IS_QSPI_XIP_INST_EN(XIP_INST_EN) (((XIP_INST_EN) == QSPI_XIP_CTRL_XIP_INST_EN) || ((XIP_INST_EN) == 0)) |
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#define IS_QSPI_INST_DDR_EN(INST_DDR_EN) (((INST_DDR_EN) == QSPI_XIP_CTRL_XIP_INST_EN) || ((INST_DDR_EN) == 0)) |
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#define IS_QSPI_DDR_EN(DDR_EN) (((DDR_EN) == QSPI_XIP_CTRL_DDR_EN) || ((DDR_EN) == 0)) |
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#define IS_QSPI_XIP_DFS_HC(XIP_DFS_HC) (((XIP_DFS_HC) == QSPI_XIP_CTRL_DFS_HC) || ((XIP_DFS_HC) == 0)) |
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#define IS_QSPI_XIP_WAIT_CYCLES(XIP_WAIT_CYCLES) ((((XIP_WAIT_CYCLES) >= QSPI_XIP_CTRL_WAIT_1CYCLES) && ((XIP_WAIT_CYCLES) <= QSPI_XIP_CTRL_WAIT_31CYCLES)) || \ |
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((XIP_WAIT_CYCLES) == 0)) |
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#define IS_QSPI_XIP_MD_BIT_EN(XIP_MD_BIT_EN) (((XIP_MD_BIT_EN) == QSPI_XIP_CTRL_MD_BIT_EN) || ((XIP_MD_BIT_EN) == 0)) |
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#define IS_QSPI_XIP_INST_L(XIP_INST_L) \ |
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(((XIP_INST_L) == QSPI_XIP_CTRL_INST_L_0_LINE) || ((XIP_INST_L) == QSPI_XIP_CTRL_INST_L_4_LINE) || \ |
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((XIP_INST_L) == QSPI_XIP_CTRL_INST_L_8_LINE) || ((XIP_INST_L) == QSPI_XIP_CTRL_INST_L_16_LINE)) |
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#define IS_QSPI_XIP_ADDR_LEN(XIP_ADDR_LEN) ((((XIP_ADDR_LEN) >= QSPI_XIP_CTRL_ADDR_4BIT) && ((XIP_ADDR_LEN) <= QSPI_XIP_CTRL_ADDR_60BIT)) || \ |
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((XIP_ADDR_LEN) == 0)) |
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#define IS_QSPI_XIP_TRANS_TYPE(XIP_TRANS_TYPE) (((XIP_TRANS_TYPE) == QSPI_XIP_CTRL_TRANS_TYPE_STANDARD_SPI) || \ |
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((XIP_TRANS_TYPE) == QSPI_XIP_CTRL_TRANS_TYPE_ADDRESS_BY_XIP_FRF) || \ |
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((XIP_TRANS_TYPE) == QSPI_XIP_CTRL_TRANS_TYPE_INSTRUCT_BY_XIP_FRF)) |
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#define IS_QSPI_XIP_FRF(XIP_FRF) (((XIP_FRF) == QSPI_XIP_CTRL_FRF_2_LINE) || ((XIP_FRF) == QSPI_XIP_CTRL_FRF_4_LINE) || ((XIP_FRF) == 0)) |
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//////////////////////////////////////////////////////////////////////////////////////////////////// |
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void QSPI_Cmd(bool cmd); |
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void QSPI_XIP_Cmd(bool cmd); |
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void QSPI_DeInit(void); |
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void QspiInitConfig(QSPI_InitType* QSPI_InitStruct); |
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void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Output); |
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void QSPI_DMA_CTRL_Config(uint8_t TxRx,uint8_t TxDataLevel,uint8_t RxDataLevel); |
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uint16_t QSPI_GetITStatus(uint16_t FLAG); |
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void QSPI_ClearITFLAG(uint16_t FLAG); |
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void QSPI_XIP_ClearITFLAG(uint16_t FLAG); |
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bool GetQspiBusyStatus(void); |
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bool GetQspiTxDataBusyStatus(void); |
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bool GetQspiTxDataEmptyStatus(void); |
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bool GetQspiRxHaveDataStatus(void); |
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bool GetQspiRxDataFullStatus(void); |
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bool GetQspiTransmitErrorStatus(void); |
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bool GetQspiDataConflictErrorStatus(void); |
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void QspiSendWord(uint32_t SendData); |
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uint32_t QspiReadWord(void); |
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uint32_t QspiGetDataPointer(void); |
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uint32_t QspiReadRxFifoNum(void); |
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void ClrFifo(void); |
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uint32_t GetFifoData(uint32_t* pData, uint32_t Len); |
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void QspiSendAndGetWords(uint32_t* pSrcData, uint32_t* pDstData, uint32_t cnt); |
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uint32_t QspiSendWordAndGetWords(uint32_t WrData, uint32_t* pRdData, uint8_t LastRd); |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /*__N32G45X_QSPI_H__ */ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/
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