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657 lines
25 KiB
657 lines
25 KiB
/***************************************************************************** |
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* Copyright (c) 2019, Nations Technologies Inc. |
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* |
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* All rights reserved. |
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* **************************************************************************** |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* - Redistributions of source code must retain the above copyright notice, |
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* this list of conditions and the disclaimer below. |
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* |
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* Nations' name may not be used to endorse or promote products derived from |
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* this software without specific prior written permission. |
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* |
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
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* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, |
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, |
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* ****************************************************************************/ |
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/** |
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* @file n32g45x_adc.h |
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* @author Nations |
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* @version v1.0.1 |
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* |
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* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. |
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*/ |
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#ifndef __N32G45X_ADC_H__ |
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#define __N32G45X_ADC_H__ |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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#include "n32g45x.h" |
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#include <stdbool.h> |
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/** @addtogroup N32G45X_StdPeriph_Driver |
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* @{ |
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*/ |
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#define VREF1P2_CTRL (*(uint32_t*)(0x40001800+0x20)) |
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#define _EnVref1p2() do{VREF1P2_CTRL|=(1<<10);}while(0); |
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#define _DisVref1p2() do{VREF1P2_CTRL&=~(1<<10);}while(0); |
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/** @addtogroup ADC |
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* @{ |
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*/ |
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/** @addtogroup ADC_Exported_Types |
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* @{ |
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*/ |
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/** |
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* @brief ADC Init structure definition |
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*/ |
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typedef struct |
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{ |
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uint32_t WorkMode; /*!< Configures the ADC to operate in independent or |
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dual mode. |
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This parameter can be a value of @ref ADC_mode */ |
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FunctionalState MultiChEn; /*!< Specifies whether the conversion is performed in |
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Scan (multichannels) or Single (one channel) mode. |
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This parameter can be set to ENABLE or DISABLE */ |
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FunctionalState ContinueConvEn; /*!< Specifies whether the conversion is performed in |
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Continuous or Single mode. |
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This parameter can be set to ENABLE or DISABLE. */ |
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uint32_t ExtTrigSelect; /*!< Defines the external trigger used to start the analog |
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to digital conversion of regular channels. This parameter |
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can be a value of @ref |
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ADC_external_trigger_sources_for_regular_channels_conversion */ |
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uint32_t DatAlign; /*!< Specifies whether the ADC data alignment is left or right. |
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This parameter can be a value of @ref ADC_data_align */ |
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uint8_t ChsNumber; /*!< Specifies the number of ADC channels that will be converted |
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using the sequencer for regular channel group. |
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This parameter must range from 1 to 16. */ |
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} ADC_InitType; |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_Exported_Constants |
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* @{ |
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*/ |
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#define IsAdcModule(PERIPH) (((PERIPH) == ADC1) || ((PERIPH) == ADC2) || ((PERIPH) == ADC3) || ((PERIPH) == ADC4)) |
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#define IsAdcDmaModule(PERIPH) (((PERIPH) == ADC1) || ((PERIPH) == ADC3)) |
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/** @addtogroup ADC_mode |
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* @{ |
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*/ |
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#define ADC_WORKMODE_INDEPENDENT ((uint32_t)0x00000000) |
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#define ADC_WORKMODE_SEQ_INJECT_SIMULT ((uint32_t)0x00010000) |
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#define ADC_WORKMODE_SEQ_SIMULT_ALTER_TRIG ((uint32_t)0x00020000) |
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#define ADC_WORKMODE_INJ_SIMULT_FAST_INTERL ((uint32_t)0x00030000) |
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#define ADC_WORKMODE_INT_SIMULT_SLOW_INTERL ((uint32_t)0x00040000) |
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#define ADC_WORKMODE_INJ_SIMULT ((uint32_t)0x00050000) |
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#define ADC_WORKMODE_REG_SIMULT ((uint32_t)0x00060000) |
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#define ADC_WORKMODE_FAST_INTERL ((uint32_t)0x00070000) |
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#define ADC_WORKMODE_SLOW_INTERL ((uint32_t)0x00080000) |
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#define ADC_WORKMODE_ALTER_TRIG ((uint32_t)0x00090000) |
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#define IsAdcWorkMode(MODE) \ |
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(((MODE) == ADC_WORKMODE_INDEPENDENT) || ((MODE) == ADC_WORKMODE_SEQ_INJECT_SIMULT) \ |
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|| ((MODE) == ADC_WORKMODE_SEQ_SIMULT_ALTER_TRIG) || ((MODE) == ADC_WORKMODE_INJ_SIMULT_FAST_INTERL) \ |
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|| ((MODE) == ADC_WORKMODE_INT_SIMULT_SLOW_INTERL) || ((MODE) == ADC_WORKMODE_INJ_SIMULT) \ |
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|| ((MODE) == ADC_WORKMODE_REG_SIMULT) || ((MODE) == ADC_WORKMODE_FAST_INTERL) \ |
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|| ((MODE) == ADC_WORKMODE_SLOW_INTERL) || ((MODE) == ADC_WORKMODE_ALTER_TRIG)) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_external_trigger_sources_for_regular_channels_conversion |
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* @{ |
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*/ |
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#define ADC_EXT_TRIGCONV_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ |
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#define ADC_EXT_TRIGCONV_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ |
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#define ADC_EXT_TRIGCONV_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ |
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#define ADC_EXT_TRIGCONV_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ |
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#define ADC_EXT_TRIGCONV_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ |
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#define ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ |
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#define ADC_EXT_TRIGCONV_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 , ADC3 and ADC4 */ |
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#define ADC_EXT_TRIGCONV_NONE ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 , ADC3 and ADC4 */ |
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#define ADC_EXT_TRIGCONV_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 and ADC4 */ |
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#define ADC_EXT_TRIGCONV_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 and ADC4 */ |
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#define ADC_EXT_TRIGCONV_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 and ADC4 */ |
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#define ADC_EXT_TRIGCONV_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 and ADC4 */ |
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#define ADC_EXT_TRIGCONV_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 and ADC4 */ |
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#define ADC_EXT_TRIGCONV_EXT_INT10_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 and ADC4 */ |
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#define IsAdcExtTrig(REGTRIG) \ |
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(((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC2) \ |
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|| ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC3) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC2) \ |
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|| ((REGTRIG) == ADC_EXT_TRIGCONV_T3_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_T4_CC4) \ |
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|| ((REGTRIG) == ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_NONE) \ |
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|| ((REGTRIG) == ADC_EXT_TRIGCONV_T3_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC3) \ |
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|| ((REGTRIG) == ADC_EXT_TRIGCONV_T8_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T8_TRGO) \ |
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|| ((REGTRIG) == ADC_EXT_TRIGCONV_T5_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_EXT_INT10_T5_CC3)) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_data_align |
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* @{ |
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*/ |
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#define ADC_DAT_ALIGN_R ((uint32_t)0x00000000) |
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#define ADC_DAT_ALIGN_L ((uint32_t)0x00000800) |
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#define IsAdcDatAlign(ALIGN) (((ALIGN) == ADC_DAT_ALIGN_R) || ((ALIGN) == ADC_DAT_ALIGN_L)) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_channels |
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* @{ |
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*/ |
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#define ADC_CH_0 ((uint8_t)0x00) |
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#define ADC_CH_1 ((uint8_t)0x01) |
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#define ADC_CH_2 ((uint8_t)0x02) |
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#define ADC_CH_3 ((uint8_t)0x03) |
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#define ADC_CH_4 ((uint8_t)0x04) |
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#define ADC_CH_5 ((uint8_t)0x05) |
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#define ADC_CH_6 ((uint8_t)0x06) |
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#define ADC_CH_7 ((uint8_t)0x07) |
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#define ADC_CH_8 ((uint8_t)0x08) |
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#define ADC_CH_9 ((uint8_t)0x09) |
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#define ADC_CH_10 ((uint8_t)0x0A) |
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#define ADC_CH_11 ((uint8_t)0x0B) |
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#define ADC_CH_12 ((uint8_t)0x0C) |
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#define ADC_CH_13 ((uint8_t)0x0D) |
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#define ADC_CH_14 ((uint8_t)0x0E) |
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#define ADC_CH_15 ((uint8_t)0x0F) |
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#define ADC_CH_16 ((uint8_t)0x10) |
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#define ADC_CH_17 ((uint8_t)0x11) |
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#define ADC_CH_18 ((uint8_t)0x12) |
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#define ADC_CH_TEMP_SENSOR ((uint8_t)ADC_CH_16) |
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#define ADC_CH_INT_VREF ((uint8_t)ADC_CH_18) |
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#define IsAdcChannel(CHANNEL) \ |
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(((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) \ |
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|| ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) \ |
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|| ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) \ |
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|| ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15) \ |
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|| ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18)) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_sampling_time |
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* @{ |
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*/ |
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#define ADC_SAMP_TIME_1CYCLES5 ((uint8_t)0x00) |
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#define ADC_SAMP_TIME_7CYCLES5 ((uint8_t)0x01) |
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#define ADC_SAMP_TIME_13CYCLES5 ((uint8_t)0x02) |
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#define ADC_SAMP_TIME_28CYCLES5 ((uint8_t)0x03) |
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#define ADC_SAMP_TIME_41CYCLES5 ((uint8_t)0x04) |
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#define ADC_SAMP_TIME_55CYCLES5 ((uint8_t)0x05) |
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#define ADC_SAMP_TIME_71CYCLES5 ((uint8_t)0x06) |
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#define ADC_SAMP_TIME_239CYCLES5 ((uint8_t)0x07) |
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#define IsAdcSampleTime(TIME) \ |
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(((TIME) == ADC_SAMP_TIME_1CYCLES5) || ((TIME) == ADC_SAMP_TIME_7CYCLES5) || ((TIME) == ADC_SAMP_TIME_13CYCLES5) \ |
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|| ((TIME) == ADC_SAMP_TIME_28CYCLES5) || ((TIME) == ADC_SAMP_TIME_41CYCLES5) \ |
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|| ((TIME) == ADC_SAMP_TIME_55CYCLES5) || ((TIME) == ADC_SAMP_TIME_71CYCLES5) \ |
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|| ((TIME) == ADC_SAMP_TIME_239CYCLES5)) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_external_trigger_sources_for_injected_channels_conversion |
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* @{ |
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*/ |
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#define ADC_EXT_TRIG_INJ_CONV_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ |
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#define ADC_EXT_TRIG_INJ_CONV_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ |
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#define ADC_EXT_TRIG_INJ_CONV_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ |
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#define ADC_EXT_TRIG_INJ_CONV_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ |
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#define ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ |
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#define ADC_EXT_TRIG_INJ_CONV_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2, ADC3 and ADC4 */ |
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#define ADC_EXT_TRIG_INJ_CONV_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2, ADC3 and ADC4 */ |
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#define ADC_EXT_TRIG_INJ_CONV_NONE ((uint32_t)0x00007000) /*!< For ADC1, ADC2, ADC3 and ADC4 */ |
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#define ADC_EXT_TRIG_INJ_CONV_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 and ADC4 */ |
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#define ADC_EXT_TRIG_INJ_CONV_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 and ADC4 */ |
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#define ADC_EXT_TRIG_INJ_CONV_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 and ADC4 */ |
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#define ADC_EXT_TRIG_INJ_CONV_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 and ADC4 */ |
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#define ADC_EXT_TRIG_INJ_CONV_EXT_INT14_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 and ADC4 */ |
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#define IsAdcExtInjTrig(INJTRIG) \ |
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(((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_CC4) \ |
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|| ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_CC1) \ |
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|| ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T3_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_TRGO) \ |
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|| ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_NONE) \ |
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|| ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_CC3) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T8_CC2) \ |
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|| ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T5_TRGO) \ |
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|| ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_EXT_INT14_T5_CC4)) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_injected_channel_selection |
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* @{ |
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*/ |
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#define ADC_INJ_CH_1 ((uint8_t)0x14) |
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#define ADC_INJ_CH_2 ((uint8_t)0x18) |
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#define ADC_INJ_CH_3 ((uint8_t)0x1C) |
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#define ADC_INJ_CH_4 ((uint8_t)0x20) |
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#define IsAdcInjCh(CHANNEL) \ |
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(((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3) \ |
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|| ((CHANNEL) == ADC_INJ_CH_4)) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_analog_watchdog_selection |
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* @{ |
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*/ |
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#define ADC_ANALOG_WTDG_SINGLEREG_ENABLE ((uint32_t)0x00800200) |
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#define ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE ((uint32_t)0x00400200) |
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#define ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE ((uint32_t)0x00C00200) |
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#define ADC_ANALOG_WTDG_ALLREG_ENABLE ((uint32_t)0x00800000) |
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#define ADC_ANALOG_WTDG_ALLINJEC_ENABLE ((uint32_t)0x00400000) |
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#define ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE ((uint32_t)0x00C00000) |
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#define ADC_ANALOG_WTDG_NONE ((uint32_t)0x00000000) |
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#define IsAdcAnalogWatchdog(WATCHDOG) \ |
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(((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE) \ |
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|| ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ENABLE) \ |
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|| ((WATCHDOG) == ADC_ANALOG_WTDG_ALLINJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE) \ |
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|| ((WATCHDOG) == ADC_ANALOG_WTDG_NONE)) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_interrupts_definition |
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* @{ |
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*/ |
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#define ADC_INT_ENDC ((uint16_t)0x0220) |
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#define ADC_INT_AWD ((uint16_t)0x0140) |
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#define ADC_INT_JENDC ((uint16_t)0x0480) |
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#define IsAdcInt(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) |
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#define IsAdcGetInt(IT) (((IT) == ADC_INT_ENDC) || ((IT) == ADC_INT_AWD) || ((IT) == ADC_INT_JENDC)) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_flags_definition |
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* @{ |
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*/ |
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#define ADC_FLAG_AWDG ((uint8_t)0x01) |
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#define ADC_FLAG_ENDC ((uint8_t)0x02) |
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#define ADC_FLAG_JENDC ((uint8_t)0x04) |
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#define ADC_FLAG_JSTR ((uint8_t)0x08) |
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#define ADC_FLAG_STR ((uint8_t)0x10) |
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#define ADC_FLAG_EOC_ANY ((uint8_t)0x20) |
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#define ADC_FLAG_JEOC_ANY ((uint8_t)0x40) |
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#define IsAdcClrFlag(FLAG) ((((FLAG) & (uint8_t)0x80) == 0x00) && ((FLAG) != 0x00)) |
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#define IsAdcGetFlag(FLAG) \ |
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(((FLAG) == ADC_FLAG_AWDG) || ((FLAG) == ADC_FLAG_ENDC) || ((FLAG) == ADC_FLAG_JENDC) || ((FLAG) == ADC_FLAG_JSTR) \ |
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|| ((FLAG) == ADC_FLAG_STR) || ((FLAG) == ADC_FLAG_EOC_ANY) || ((FLAG) == ADC_FLAG_JEOC_ANY)) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_thresholds |
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* @{ |
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*/ |
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#define IsAdcValid(THRESHOLD) ((THRESHOLD) <= 0xFFF) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_injected_offset |
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* @{ |
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*/ |
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#define IsAdcOffsetValid(OFFSET) ((OFFSET) <= 0xFFF) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_injected_length |
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* @{ |
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*/ |
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#define IsAdcInjLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_injected_rank |
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* @{ |
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*/ |
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#define IsAdcInjRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_regular_length |
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* @{ |
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*/ |
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#define IsAdcSeqLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_regular_rank |
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* @{ |
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*/ |
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#define IsAdcReqRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_regular_discontinuous_mode_number |
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* @{ |
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*/ |
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#define IsAdcSeqDiscNumberValid(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) |
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/** |
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* @} |
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*/ |
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/************************** fllowing bit seg in ex register **********************/ |
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/**@addtogroup ADC_channels_ex_style |
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* @{ |
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*/ |
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#define ADC1_Channel_01_PA0 ((uint8_t)0x01) |
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#define ADC1_Channel_02_PA1 ((uint8_t)0x02) |
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#define ADC1_Channel_03_PA6 ((uint8_t)0x03) |
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#define ADC1_Channel_04_PA3 ((uint8_t)0x04) |
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#define ADC1_Channel_05_PF4 ((uint8_t)0x05) |
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#define ADC1_Channel_06_PC0 ((uint8_t)0x06) |
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#define ADC1_Channel_07_PC1 ((uint8_t)0x07) |
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#define ADC1_Channel_08_PC2 ((uint8_t)0x08) |
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#define ADC1_Channel_09_PC3 ((uint8_t)0x09) |
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#define ADC1_Channel_10_PF2 ((uint8_t)0x0A) |
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#define ADC1_Channel_11_PA2 ((uint8_t)0x0B) |
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#define ADC2_Channel_01_PA4 ((uint8_t)0x01) |
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#define ADC2_Channel_02_PA5 ((uint8_t)0x02) |
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#define ADC2_Channel_03_PB1 ((uint8_t)0x03) |
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#define ADC2_Channel_04_PA7 ((uint8_t)0x04) |
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#define ADC2_Channel_05_PC4 ((uint8_t)0x05) |
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#define ADC2_Channel_06_PC0 ((uint8_t)0x06) |
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#define ADC2_Channel_07_PC1 ((uint8_t)0x07) |
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#define ADC2_Channel_08_PC2 ((uint8_t)0x08) |
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#define ADC2_Channel_09_PC3 ((uint8_t)0x09) |
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#define ADC2_Channel_10_PF2 ((uint8_t)0x0A) |
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#define ADC2_Channel_11_PA2 ((uint8_t)0x0B) |
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#define ADC2_Channel_12_PC5 ((uint8_t)0x0C) |
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#define ADC2_Channel_13_PB2 ((uint8_t)0x0D) |
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#define ADC3_Channel_01_PB11 ((uint8_t)0x01) |
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#define ADC3_Channel_02_PE9 ((uint8_t)0x02) |
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#define ADC3_Channel_03_PE13 ((uint8_t)0x03) |
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#define ADC3_Channel_04_PE12 ((uint8_t)0x04) |
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#define ADC3_Channel_05_PB13 ((uint8_t)0x05) |
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#define ADC3_Channel_06_PE8 ((uint8_t)0x06) |
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#define ADC3_Channel_07_PD10 ((uint8_t)0x07) |
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#define ADC3_Channel_08_PD11 ((uint8_t)0x08) |
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#define ADC3_Channel_09_PD12 ((uint8_t)0x09) |
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#define ADC3_Channel_10_PD13 ((uint8_t)0x0A) |
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#define ADC3_Channel_11_PD14 ((uint8_t)0x0B) |
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#define ADC3_Channel_12_PB0 ((uint8_t)0x0C) |
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#define ADC3_Channel_13_PE7 ((uint8_t)0x0D) |
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#define ADC3_Channel_14_PE10 ((uint8_t)0x0E) |
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#define ADC3_Channel_15_PE11 ((uint8_t)0x0F) |
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#define ADC4_Channel_01_PE14 ((uint8_t)0x01) |
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#define ADC4_Channel_02_PE15 ((uint8_t)0x02) |
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#define ADC4_Channel_03_PB12 ((uint8_t)0x03) |
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#define ADC4_Channel_04_PB14 ((uint8_t)0x04) |
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#define ADC4_Channel_05_PB15 ((uint8_t)0x05) |
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#define ADC4_Channel_06_PE8 ((uint8_t)0x06) |
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#define ADC4_Channel_07_PD10 ((uint8_t)0x07) |
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#define ADC4_Channel_08_PD11 ((uint8_t)0x08) |
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#define ADC4_Channel_09_PD12 ((uint8_t)0x09) |
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#define ADC4_Channel_10_PD13 ((uint8_t)0x0A) |
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#define ADC4_Channel_11_PD14 ((uint8_t)0x0B) |
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#define ADC4_Channel_12_PD8 ((uint8_t)0x0C) |
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#define ADC4_Channel_13_PD9 ((uint8_t)0x0D) |
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#define ADC_CH_0 ((uint8_t)0x00) |
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#define ADC_CH_1 ((uint8_t)0x01) |
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#define ADC_CH_2 ((uint8_t)0x02) |
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#define ADC_CH_3 ((uint8_t)0x03) |
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#define ADC_CH_4 ((uint8_t)0x04) |
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#define ADC_CH_5 ((uint8_t)0x05) |
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#define ADC_CH_6 ((uint8_t)0x06) |
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#define ADC_CH_7 ((uint8_t)0x07) |
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#define ADC_CH_8 ((uint8_t)0x08) |
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#define ADC_CH_9 ((uint8_t)0x09) |
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#define ADC_CH_10 ((uint8_t)0x0A) |
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#define ADC_CH_11 ((uint8_t)0x0B) |
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#define ADC_CH_12 ((uint8_t)0x0C) |
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#define ADC_CH_13 ((uint8_t)0x0D) |
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#define ADC_CH_14 ((uint8_t)0x0E) |
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#define ADC_CH_15 ((uint8_t)0x0F) |
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#define ADC_CH_16 ((uint8_t)0x10) |
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#define ADC_CH_17 ((uint8_t)0x11) |
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#define ADC_CH_18 ((uint8_t)0x12) |
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/** |
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* @} |
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*/ |
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/**@addtogroup ADC_dif_sel_ch_definition |
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* @{ |
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*/ |
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#define ADC_DIFSEL_CHS_MASK ((uint32_t)0x0007FFFE) |
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#define ADC_DIFSEL_CHS_1 ((uint32_t)0x00000002) |
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#define ADC_DIFSEL_CHS_2 ((uint32_t)0x00000004) |
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#define ADC_DIFSEL_CHS_3 ((uint32_t)0x00000008) |
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#define ADC_DIFSEL_CHS_4 ((uint32_t)0x00000010) |
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#define ADC_DIFSEL_CHS_5 ((uint32_t)0x00000020) |
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#define ADC_DIFSEL_CHS_6 ((uint32_t)0x00000040) |
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#define ADC_DIFSEL_CHS_7 ((uint32_t)0x00000080) |
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#define ADC_DIFSEL_CHS_8 ((uint32_t)0x00000100) |
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#define ADC_DIFSEL_CHS_9 ((uint32_t)0x00000200) |
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#define ADC_DIFSEL_CHS_10 ((uint32_t)0x00000400) |
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#define ADC_DIFSEL_CHS_11 ((uint32_t)0x00000800) |
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#define ADC_DIFSEL_CHS_12 ((uint32_t)0x00001000) |
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#define ADC_DIFSEL_CHS_13 ((uint32_t)0x00002000) |
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#define ADC_DIFSEL_CHS_14 ((uint32_t)0x00004000) |
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#define ADC_DIFSEL_CHS_15 ((uint32_t)0x00008000) |
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#define ADC_DIFSEL_CHS_16 ((uint32_t)0x00010000) |
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#define ADC_DIFSEL_CHS_17 ((uint32_t)0x00020000) |
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#define ADC_DIFSEL_CHS_18 ((uint32_t)0x00040000) |
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/** |
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* @} |
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*/ |
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/**@addtogroup ADC_calfact_definition |
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* @{ |
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*/ |
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#define ADC_CALFACT_CALFACTD_MSK ((uint32_t)0x3FL << 16) |
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#define ADC_CALFACT_CALFACTS_MSK ((uint32_t)0x3FL << 0) |
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/** |
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* @} |
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*/ |
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/**@addtogroup ADC_ctrl3_definition |
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* @{ |
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*/ |
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#define ADC_CTRL3_VABTMEN_MSK ((uint32_t)0x01L << 11) |
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#define ADC_CTRL3_DPWMOD_MSK ((uint32_t)0x01L << 10) |
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#define ADC_CTRL3_JENDCAIEN_MSK ((uint32_t)0x01L << 9) |
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#define ADC_CTRL3_ENDCAIEN_MSK ((uint32_t)0x01L << 8) |
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#define ADC_CTRL3_BPCAL_MSK ((uint32_t)0x01L << 7) |
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#define ADC_CTRL3_PDRDY_MSK ((uint32_t)0x01L << 6) |
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#define ADC_CTRL3_RDY_MSK ((uint32_t)0x01L << 5) |
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#define ADC_CTRL3_CKMOD_MSK ((uint32_t)0x01L << 4) |
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#define ADC_CTRL3_CALALD_MSK ((uint32_t)0x01L << 3) |
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#define ADC_CTRL3_CALDIF_MSK ((uint32_t)0x01L << 2) |
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#define ADC_CTRL3_RES_MSK ((uint32_t)0x03L << 0) |
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/** |
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* @} |
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*/ |
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/**@addtogroup ADC_sampt3_definition |
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* @{ |
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*/ |
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#define ADC_SAMPT3_SAMPSEL_MSK ((uint32_t)0x01L << 3) |
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/** |
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* @} |
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*/ |
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typedef enum |
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{ |
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ADC_CTRL3_CKMOD_AHB = 0, |
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ADC_CTRL3_CKMOD_PLL = 1, |
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} ADC_CTRL3_CKMOD; |
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typedef enum |
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{ |
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ADC_CTRL3_RES_12BIT = 3, |
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ADC_CTRL3_RES_10BIT = 2, |
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ADC_CTRL3_RES_8BIT = 1, |
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ADC_CTRL3_RES_6BIT = 0, |
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} ADC_CTRL3_RES; |
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typedef struct |
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{ |
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FunctionalState VbatMinitEn; |
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FunctionalState DeepPowerModEn; |
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FunctionalState JendcIntEn; |
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FunctionalState EndcIntEn; |
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ADC_CTRL3_CKMOD ClkMode; |
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FunctionalState CalAtuoLoadEn; |
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bool DifModCal; |
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ADC_CTRL3_RES ResBit; |
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bool SampSecondStyle; |
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} ADC_InitTypeEx; |
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/** |
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* @} |
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*/ |
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/*ADC_SAMPT3 only have samp time and smp18[2:0],samp18 is refint ch, change to row function*/ |
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/*ADC_IPTST reseverd register ,not to do it*/ |
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/**@addtogroup ADC_bit_num_definition |
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* @{ |
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*/ |
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#define ADC_RST_BIT_12 ((uint32_t)0x03) |
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#define ADC_RST_BIT_10 ((uint32_t)0x02) |
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#define ADC_RST_BIT_8 ((uint32_t)0x01) |
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#define ADC_RESULT_BIT_6 ((uint32_t)0x00) |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_flags_ex_definition |
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* @{ |
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*/ |
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#define ADC_FLAG_RDY ((uint8_t)0x20) |
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#define ADC_FLAG_PD_RDY ((uint8_t)0x40) |
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#define IS_ADC_GET_READY(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_PD_RDY) |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/** @addtogroup ADC_Exported_Functions |
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* @{ |
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*/ |
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void ADC_DeInit(ADC_Module* ADCx); |
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void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct); |
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void ADC_InitStruct(ADC_InitType* ADC_InitStruct); |
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void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd); |
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void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd); |
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void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd); |
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void ADC_StartCalibration(ADC_Module* ADCx); |
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FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx); |
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void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd); |
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FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx); |
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void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number); |
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void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd); |
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void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); |
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void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd); |
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uint16_t ADC_GetDat(ADC_Module* ADCx); |
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uint32_t ADC_GetDualModeConversionDat(ADC_Module* ADCx); |
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void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); |
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void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd); |
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void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv); |
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void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); |
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void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); |
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FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx); |
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void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); |
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void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length); |
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void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); |
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uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel); |
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void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog); |
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void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); |
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void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel); |
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void ADC_EnableTempSensorVrefint(FunctionalState Cmd); |
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FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG); |
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void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG); |
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INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT); |
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void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT); |
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void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx); |
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void ADC_SetDifChs(ADC_Module* ADCx,uint32_t DifChs); |
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FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW); |
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void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en); |
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void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum); |
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void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler); |
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/** |
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* @} |
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*/ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /*__N32G45X_ADC_H__ */ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/
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