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422 lines
13 KiB
422 lines
13 KiB
2 days ago
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/*****************************************************************************
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* Copyright (c) 2019, Nations Technologies Inc.
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*
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* All rights reserved.
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* ****************************************************************************
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Nations' name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ****************************************************************************/
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/**
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* @file system_n32g45x.c
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* @author Nations
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* @version v1.0.1
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*
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* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
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*/
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#include "n32g45x.h"
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/* Uncomment the line corresponding to the desired System clock (SYSCLK)
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frequency (after reset the HSI is used as SYSCLK source)
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IMPORTANT NOTE:
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==============
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1. After each device reset the HSI is used as System clock source.
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2. Please make sure that the selected System clock doesn't exceed your
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device's maximum frequency.
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3. If none of the define below is enabled, the HSI is used as System clock
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source.
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4. The System clock configuration functions provided within this file assume
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that:
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- For Low, Medium and High density Value line devices an external 8MHz
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crystal is used to drive the System clock.
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- For Low, Medium and High density devices an external 8MHz crystal is
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used to drive the System clock.
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- For Connectivity line devices an external 25MHz crystal is used to
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drive the System clock. If you are using different crystal you have to adapt
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those functions accordingly.
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*/
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#define SYSCLK_USE_HSI 0
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#define SYSCLK_USE_HSE 1
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#define SYSCLK_USE_HSI_PLL 2
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#define SYSCLK_USE_HSE_PLL 3
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#ifndef SYSCLK_FREQ
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#define SYSCLK_FREQ 144000000
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#endif
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#ifndef SYSCLK_SRC
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#define SYSCLK_SRC SYSCLK_USE_HSE_PLL
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#endif
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#if SYSCLK_SRC == SYSCLK_USE_HSI
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#if SYSCLK_FREQ != HSI_VALUE
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#error SYSCL_FREQ must be set to HSI_VALUE
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#endif
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#elif SYSCLK_SRC == SYSCLK_USE_HSE
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#ifndef HSE_VALUE
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#error HSE_VALUE must be defined!
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#endif
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#if SYSCLK_FREQ != HSE_VALUE
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#error SYSCL_FREQ must be set to HSE_VALUE
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#endif
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#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL
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#if (SYSCLK_FREQ % (HSI_VALUE / 2) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 2) >= 2) \
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&& (SYSCLK_FREQ / (HSI_VALUE / 2) <= 32)
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#define PLLSRC_DIV 2
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#define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 2))
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#else
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#error Cannot make a PLL multiply factor to SYSCLK_FREQ.
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#endif
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#elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL
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#ifndef HSE_VALUE
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#error HSE_VALUE must be defined!
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#endif
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#if ((SYSCLK_FREQ % (HSE_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 2) >= 2) \
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&& (SYSCLK_FREQ / (HSE_VALUE / 2) <= 32)
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#define PLLSRC_DIV 2
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#define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 2))
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#elif (SYSCLK_FREQ % HSE_VALUE == 0) && (SYSCLK_FREQ / HSE_VALUE >= 2) && (SYSCLK_FREQ / HSE_VALUE <= 32)
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#define PLLSRC_DIV 1
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#define PLL_MUL (SYSCLK_FREQ / HSE_VALUE)
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#else
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#error Cannot make a PLL multiply factor to SYSCLK_FREQ.
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#endif
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#else
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#error wrong value for SYSCLK_SRC
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#endif
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */
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/*******************************************************************************
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* Clock Definitions
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*******************************************************************************/
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uint32_t SystemCoreClock = SYSCLK_FREQ; /*!< System Clock Frequency (Core Clock) */
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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static void SetSysClock(void);
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#ifdef DATA_IN_ExtSRAM
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static void SystemInit_ExtMemCtl(void);
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#endif /* DATA_IN_ExtSRAM */
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemCoreClock variable.
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* @note This function should be used only after reset.
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*/
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void SystemInit(void)
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{
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/* FPU settings
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* ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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/* Set HSIEN bit */
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RCC->CTRL |= (uint32_t)0x00000001;
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/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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RCC->CFG &= (uint32_t)0xF8FFC000;
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/* Reset HSEON, CLKSSEN and PLLEN bits */
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RCC->CTRL &= (uint32_t)0xFEF6FFFF;
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/* Reset HSEBYP bit */
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RCC->CTRL &= (uint32_t)0xFFFBFFFF;
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/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRES/OTGFSPRE bits */
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RCC->CFG &= (uint32_t)0xF700FFFF;
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/* Reset CFG2 register */
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RCC->CFG2 = 0x00000000;
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/* Reset CFG3 register */
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RCC->CFG3 = 0x00000000;
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/* Disable all interrupts and clear pending bits */
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RCC->CLKINT = 0x009F0000;
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/* Enable ex mode */
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RCC->APB1PCLKEN |= RCC_APB1PCLKEN_PWREN;
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PWR->CTRL3 |= 0x00000001;
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RCC->APB1PCLKEN &= (uint32_t)(~RCC_APB1PCLKEN_PWREN);
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/* Enable ICACHE and Prefetch Buffer */
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FLASH->AC |= (uint32_t)(FLASH_AC_ICAHEN | FLASH_AC_PRFTBFEN);
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#ifdef DATA_IN_ExtSRAM
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM */
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/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
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/* Configure the Flash Latency cycles and enable prefetch buffer */
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SetSysClock();
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or
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* configure other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any
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* configuration based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the
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* HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the
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* HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the
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* HSE_VALUE(**) or HSI_VALUE(*) multiplied by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in n32g45x.h file (default value
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* 8 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in N32G45X.h file (default value
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* 8 MHz or 25 MHz, depedning on the product used), user has to
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* ensure that HSE_VALUE is same as the real frequency of the crystal used.
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* Otherwise, this function may have wrong result.
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*
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* - The result of this function could be not correct when using
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* fractional value for HSE crystal.
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp = 0, pllmull = 0, pllsource = 0;
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/* Get SYSCLK source
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* -------------------------------------------------------*/
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tmp = RCC->CFG & RCC_CFG_SCLKSTS;
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switch (tmp)
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{
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case 0x00: /* HSI used as system clock */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04: /* HSE used as system clock */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08: /* PLL used as system clock */
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/* Get PLL clock source and multiplication factor
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* ----------------------*/
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pllmull = RCC->CFG & RCC_CFG_PLLMULFCT;
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pllsource = RCC->CFG & RCC_CFG_PLLSRC;
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if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0)
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{
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pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0
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}
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else
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{
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pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1
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}
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if (pllsource == 0x00)
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{
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/* HSI oscillator clock divided by 2 selected as PLL clock entry */
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SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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}
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else
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{
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/* HSE selected as PLL clock entry */
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if ((RCC->CFG & RCC_CFG_PLLHSEPRES) != (uint32_t)RESET)
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{ /* HSE oscillator clock divided by 2 */
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SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
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}
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else
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{
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SystemCoreClock = HSE_VALUE * pllmull;
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}
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}
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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/* Compute HCLK clock frequency ----------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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/**
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* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1
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* prescalers.
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*/
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static void SetSysClock(void)
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{
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uint32_t rcc_cfgr = 0;
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bool HSEStatus = 0;
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uint32_t StartUpCounter = 0;
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#if SYSCLK_SRC == SYSCLK_USE_HSE || SYSCLK_SRC == SYSCLK_USE_HSE_PLL
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/* Enable HSE */
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RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTRL & RCC_CTRL_HSERDF;
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StartUpCounter++;
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} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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HSEStatus = ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET);
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if (!HSEStatus)
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{
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/* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error */
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SystemCoreClock = HSI_VALUE;
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return;
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}
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#endif
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/* Flash wait state
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0: HCLK <= 32M
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1: HCLK <= 64M
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2: HCLK <= 96M
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3: HCLK <= 128M
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4: HCLK <= 144M
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*/
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FLASH->AC &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY);
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FLASH->AC |= (uint32_t)((SYSCLK_FREQ - 1) / 32000000);
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/* HCLK = SYSCLK */
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RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1;
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/* PCLK2 max 72M */
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if (SYSCLK_FREQ > 72000000)
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{
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RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2;
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}
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else
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{
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RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV1;
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}
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/* PCLK1 max 36M */
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if (SYSCLK_FREQ > 72000000)
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{
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RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4;
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}
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else if (SYSCLK_FREQ > 36000000)
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{
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RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV2;
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}
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else
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{
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RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV1;
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}
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#if SYSCLK_SRC == SYSCLK_USE_HSE
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/* Select HSE as system clock source */
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RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
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RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSE;
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/* Wait till HSE is used as system clock source */
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while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x04)
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{
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}
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#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL || SYSCLK_SRC == SYSCLK_USE_HSE_PLL
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/* clear bits */
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RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT));
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/* set PLL source */
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rcc_cfgr = RCC->CFG;
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rcc_cfgr |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI_DIV2 : RCC_CFG_PLLSRC_HSE);
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#if SYSCLK_SRC == SYSCLK_USE_HSE_PLL
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rcc_cfgr |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2);
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#endif
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/* set PLL multiply factor */
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#if PLL_MUL <= 16
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rcc_cfgr |= (PLL_MUL - 2) << 18;
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#else
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rcc_cfgr |= ((PLL_MUL - 17) << 18) | (1 << 27);
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#endif
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RCC->CFG = rcc_cfgr;
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/* Enable PLL */
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RCC->CTRL |= RCC_CTRL_PLLEN;
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/* Wait till PLL is ready */
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||
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while ((RCC->CTRL & RCC_CTRL_PLLRDF) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
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RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_PLL;
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|
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||
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/* Wait till PLL is used as system clock source */
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||
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while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x08)
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||
|
{
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||
|
}
|
||
|
#endif
|
||
|
}
|